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project engineering interns

Salary undisclosed

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Original
Simplified
  • Design LV electrical
  • Create drawing GA SLD schematic, making BOM and SR
Qualifications

  • Familiar with AutoCad or Creo software is a must
  • A must active student university status with max semester 8
  • Willing to be place in Cikarang Plant for 6 months length


Schedule: Part-time
Req: 00926O
  • Design LV electrical
  • Create drawing GA SLD schematic, making BOM and SR
Qualifications

  • Familiar with AutoCad or Creo software is a must
  • A must active student university status with max semester 8
  • Willing to be place in Cikarang Plant for 6 months length


Schedule: Part-time
Req: 00926O