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RTL Design Engineer

Salary undisclosed

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Job Description:

  • Lead the design and development of RTL code for complex digital systems.
  • Collaborate with cross-functional teams to define and implement design features and enhancements.
  • Optimize design performance, power, and area (PPA) metrics.
  • Write constraints for synthesis and timing analysis.
  • Develop and maintain high-level and micro-architectural specifications.
  • Review verification plans and coverage reports.
  • Work with test teams to implement all the required features for DFT, DFD, etc.
  • Write functional and timing ECOs.
  • Write RTL assertions and unit-level tests.
  • Collaborate with firmware and software teams to ensure seamless integration of design features.
  • Provide technical leadership and mentorship to junior engineers.
  • Stay updated with the latest advancements in digital design technologies and industry trends.

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Extensive experience in RTL design and development.
  • Proficiency in RTL coding using Verilog and System Verilog.
  • Experience with power optimization, synthesis, and timing closure methodologies.
  • Knowledge of design for test (DFT) and design for debug (DFD) techniques.
  • Familiarity with simulation and emulation tools.
  • Excellent problem-solving and analytical skills.
  • Strong communication and teamwork skill

Job Type

Regular

Shift

Shift 1 (India)

Primary Location:

Ecospace 1

Additional Locations:

Penang 14, Penang 15, Penang 16

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.